Electronics Lab

Read out draw currently in use.

Current Read out Drivers

The ATLAS detector records proton-proton collisions provided by the Large Hadron Collider (LHC) at CERN. These collisions are recorded every 50 ns (or 20 MHz frequency) leading to data flows of 10 Pb/s (1 Pb is 106 Gb). These data flows are far above the capabilities of today’s conventional computing and network technologies. As a result, a very small fraction of these data (less than 1 in 106 events) can be kept for further analysis in conventional computing farms. In order to achieve this rejection, very fast decisions need to be made on the basis processing of large data volumes in order to decide what data to keep and what data to further transfer. This is accomplished with dedicated devices: high-throughput electronics. The upgraded LHC will provide collisions at rates that will be at least 10 times higher than those of today. This imposes new challenges for which new, more advanced designs are required.


The ATLAS group at Wits is developing a high-throughput electronics laboratory on campus. High-throughput electronics deals with massive transfer of data at very high rates in challenging environments. Very fast decisions need to be exercised in order to select of modify large amounts of data at high rates.  These would include environments with high level of radiation, possible event upsets and other factors that may produce data corruption. In these conditions data monitoring, error identification and recovery are tasks that are performed as the data is transferred and formatted for further processing by higher-level units. This laboratory will serve the needs for upgrade of the ATLAS detector and more specifically, the Tile Calorimeter and the Silicon Strip sub-detectors. Both sub-detectors enjoy strong commonalities in the way data is transferred and how the off-detector electronics are designed. Same infrastructure and technical assistance can be used for both sets of projects.


The picture to the right is the current Read out Drivers (ROD) in use.


The pictures below are two views of the proposed layout of the electronics lab. Click here to see more.



Maintenance and Operations:

Upgrade Activities:

Single Event Upsets (SEU) and Reliability    top ↑

Low voltage power supply

A study of Single Event Upsets (SEU) was performed on a commercial pulse-width modulator controller chip for switching power supplies. We performed tests to study the probability of an SEU occurring as a function of incident particle(hadron) energy. A SEU in this context is a radiation induced software error that, due to the nature of the radiation, is random. We discuss the performance of the circuit, and present a solution using external circuitry to effectively eliminate the effect.


After a comprehensive set of radiation tolerance measurements to qualify the new switching power supply for the ATLAS TileCal front-end electronics. We discovered a sensitivity to single event upsets. This was surprising since the previous design had been measured for SEU tolerance and found to be satisfactory, and since we used mostly the same parts in the new design. Our studies over the course of a year identified the cause being a flip flop in the controller chip. Fortunately, we were able to find a fix for this in the design before going into production. We also showed that there is an energy dependence of SEUs in this design. This study underscores the importance of specifying the energy range of interest for SEU tolerance, which will be dependent on the environment.


The full article can be found here.

A poster of the study can be found here.

MobiDICK   top ↑

The Mobile Drawer Integrity Checking (MobiDICK) system is a mobile version of the TileCal super-drawer test bench which was used during the electronics production. In its first version, the MobiDICK system was used to fully qualify the super-drawers during commissioning of the detector and refurbishment campaigns. The MobieDick is now in its fourth generation called MobiDICK4. The fourth generation of the system, aims to provide more functionality to the system and a long term replacement for the other test-benches which rely on obsolete technologies.


The new MobiDick4 includes several state-of-the-art daugther-boards which provide different functionality to the motherboard: ADC trigger read-out, CAN bus interface, HV power supply and LED pulse generator. An additional daughter-board is required to distribute power to all the boards, and an external ATX power supply is needed to power the super-drawer electronics. The Wits HEP group has participated in the upgrade of two of these daughter-boards namely the HV and LED boards. We are redesigning the boards to include all the recent upgrades and patches to the current boards so they become permanent fixes.


  • HV Board (Redesigned by WITS)   top ↑

    High Voltage Board
    The High Voltage board is used to power the Photo Multiplier Tubes (PMTs) which are used in the simulation of data taking in order to test the front end electronics. The HV board is located inside the MobiDICK4. An optocoupler was patched onto the design to isolate the board from the main motherboard due to a malfunction of the HV power up sequence causing components on the main board to burn out. This patch has been added to the board in the new design. The LED indicators on the board were also replaced with cable connectors so that the status LEDs could be placed further away from the board in a more user friendly location.
  • The redesign of the HV board by the University of the Witwatersrand was done in two phases:

  • LED Board   top ↑

    The LED Board

    The LED board has the function of simulating an event in the detector by sending a pulse of light (the light simulates a particle passing through the scintillator). This light is converted into a very weak voltage which is in turn "boosted" by the PMTs. The PMTs are powered by the HV Board described above. This LED board acts as a trigger board and is called the LED Driver.


    The trigger input is a TTL pulse of 100ns. The technology is rather dated and this results in spare components being difficult to find. We are currently looking into options for replacing a large number of components by a new single chip which has the same functionality. This will dramatically reduce the size of the board and simplify the design.

Prototyping (click here)

Super Read Out Drivers (sROD)   top ↑

Architecture of the SROD
The TileCal ROD is the core element of the back-end electronics. Each board reads out 8 super-drawer modules through dedicated front-end optical links at a maximum rate of 100 kHz and transfer speed of 640 Mb/s. Up to 64 ROD modules distributed across four crates are necessary to read-out the total of 256 super-drawers in TileCal. The ROD is a high-throughput system based on the combination of Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). The ROD is capable of sustaining large data throughputs and to perform sophisticated operations at rates that are not possible with conventional computers. The design of the RODs presently used by ATLAS to take data was finalized about a decade ago. The performance of FPGAs has greatly improved since then. This secures the feasibility of the new requirements of the ATLAS upgrade.


The ATLAS detector at CERN has been dealing with problems of high-throughput electronics and computing for about 20 years. The experience in designing, prototyping and massive production is vast. The academic staff of the Wits-ATLAS group has many years of experience in this particular area, as well. The Wits-ATLAS group has taken the first steps to build up the core hardware infrastructure for prototype development with the purchase of two critical elements. The GLIB card and the ATCA.

  • Glib

    GLIB Card to be used

    The GLIB   top ↑

    Gigabit Link Interface Board (GLIB, see picture on the right). This module is an evaluation platform and an easy entry point for users of high-speed optical links in high-energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory to control, triggering and data acquisition from remote modules in beam or irradiation tests. The module depicted in the Figure incorporates one of the fastest FPGAs in the market. This card plays a strong role in the R&D work necessary for the establishment of the first demonstrator of the future fast read-out electronics for ATLAS sROD.
  • Actual ATCA crate at CERN

    The ATCA   top ↑

    Advanced Telecommunications Computing Architecture system (ATCA, see picture on the left). This system is composed of a chassis and a dedicated carrier for the GLIB module. The ATCA system has now become a universal interface for electronics and it needs to be mastered by researches. All electronics prototypes and future read-out systems will be interfaced though ATCA systems. This system will be required for the development, maintenance and operations of the readout electronics of ATLAS and numerous other applications in sciences and industry.
  • A setup composed of a GLIB module mounted on an ATCA system has been recently established at CERN. PhD students are currently learning the setup in order to replicate it by August of 2013 at Wits.

  • The sROD Design   top ↑

    PCB Layout of the sROD

    The LHC upgrade Phase-II will imply a complete redesign of the read-out electronics in TileCal. In the proposed new read-out architecture, the front-end electronics will transmit full digitized information to the back-end system. Besides performing the data read-out, the back-end system will provide digital calibrated information to the first level trigger. The Upgrade Demonstrator is a project envisaged to qualify this new architecture: During 2014, a reduced part of the detector (one of its 256 modules) will be equipped with the new electronics to evaluate the proposed architecture in real conditions.


    The upgraded Read-Out Driver (sROD) will be the core element of the back-end electronics in Phase-II. It is designed on a double mid-size AMC format and will operate under an AdvancedTCA framework. As processing elements, the sROD module includes two Xilinx Series 7 Field Programmable Gate Arrays (FPGAs) equipped with MultiGigabit Transceivers (MGTs). These devices are used for data receiving and processing from the front-electronics as well as to send control and configuration commands to it. Parallel Flash and DDR3 memories allow the storage of the FPGA configuration files and the implementation of embedded systems. The sROD module includes one 10/100/1000 Ethernet port and one slot for a FPGA Mezzanine Card (FMC) to extend its functionalities. Different optical connectors provide communication capabilities to the board: four QSFP+ modules for uplink and downlink transmission to the front-end electronics, one Avago MiniPOD transmitter for the communication with the first level trigger (L1-Calo system), one SFP+ module to maintain backward compatibility with the present architecture and one Avago MiniPOD receiver for expansion functionalities. Power connection to the ATCA carrier or uTCA platform is managed by the Module Management Controller (MMC) mezzanine which implements the Intelligent Platform Management Interface (IPMI) communication standard to manage the hot swap power sequence with the ATCA system.


  • Concept and Design (Click Here)

Wits HEP Group, School of Physics,
University of the Witwatersrand,
1 Jan Smuts Ave, Johannesburg, South Africa
Telephone: +27 11 717 6848
Fax: +27 11 717 6879