The LHC upgrade Phase-II will imply a complete redesign of the read-out electronics in TileCal, in order to cope with the luminosity increase by a factor of ten at 2022. In the proposed new read-out architecture, the front-end electronics will transmit full digitized information to the back-end system. Besides performing the data read-out, the back-end system will provide digital calibrated information to the first level trigger. The change on the level 1 boundary, together with introduced redundancy on the data links, imply a considerable increase of the detector output bandwidth.
The Upgrade Demonstrator is a project envisaged to qualify this new architecture: During 2014, a reduced part of the detector (one of its 256 modules) will be equipped with the new electronics to evaluate the proposed architecture in real conditions. Electronics within this module will be hybrid in order to maintain compatibility with the present system, and will provide both analog and digital trigger signals.